(1) Field of the Invention
This invention relates to a method and program for designing semiconductor integrated circuits having a plurality of clock modes and, more particularly, to a method and program for designing semiconductor integrated circuits which can optimize clock skews on a plurality of clock paths in each clock mode.
(2) Description of the Related Art
In recent years the integration levels of LSIs have been increased and they have become minuter. With this, processing by one LSI has become large in scale and LSIs more complicated and sophisticated than conventional ones can be realized. Clock signals more complicated than conventional ones are used in many of these sophisticated LSIs. For example, there are LSIs having a plurality of clock modes, such as a clock signal usually used and a clock signal used to perform a test. Gated clock circuits or the like which cut off the supply of clock signals except the period during which a flip-flop updates data are also used as a method for reducing consumption of power.
However, if clock signals are complicatedly used in this way, a clock skew may increase due to an increase in the number of gates on a path, an increase in load, and the like and normal clock timing may not be obtained at, for example, a flip-flop circuit in a circuit. Timing correction for clock skews is needed for each clock signal, especially if a circuit has a plurality of clock modes.
Conventionally, optimization has usually been performed in one of a plurality of clock modes to determine the layout when a circuit having these clock modes is designed. Therefore, when this circuit operates in another clock mode, a path on which a new timing error occurs may appear. With some sophisticated LSIs, it is very difficult to cause clock timing to match in all clock modes. Conventionally, in such a case a designer has manually performed a skew adjustment in each clock mode. As a result, a great many man-hours have been needed.
FIG. 10 is a view showing an example of the circuit structure of an LSI having a plurality of clock modes.
In FIG. 10, an example of the circuit structure of a part of the input end of an LSI is shown. Two clock signals are supplied to this circuit. That is to say, a clock signal CLK usually used and a test clock signal TCK used to test the operation of the circuit are supplied. A clock signal CLK branches via a cell C71. One is supplied clock signal CLK branches via a cell C71. One is supplied to an input terminal A72 of a selector S72 and the other is supplied to an input terminal A74 of a selector S74 via an OR gate G73. A test clock signal TCK branches via a cell C75. One is supplied to an input terminal B72 of the selector S72 and the other is supplied to an input terminal B74 of the selector S74.
A test signal TST is supplied both to the selector S72 and to the selector S74 via a cell C76. Switching between output of a clock signal CLK and a test clock signal TCK is performed by this test signal TST. As a result, a clock mode is switched.
A signal output from an output terminal X72 of the selector S72 branches via cells C77 and C78 and is input to clock input of flip-flop circuits FF79 and FF80. A signal output from the selector S74 branches via a cell C81 and is input to clock input of flip-flop circuits FF82 and FF83. A signal output from the flip-flop circuit FF80 is input to data input of the flip-flop circuit FF83. A signal output from the flip-flop circuit FF82 is input to data input of the flip-flop circuit FF79.
A control signal EN is input to the other input terminal B73 of the OR gate G73 to which a clock signal CLK is input, so that a gated clock circuit is formed. That is to say, when a control signal EN at the H level is input at normal operation time, a clock signal CLK output to the flip-flop circuits FF82 and FF83 is kept at the H level and the update of data output from the flip-flop circuits FF82 and FF83 is stopped.
It is assumed that a signal path for a clock signal CLK from input through the cell C71, selector S72, and cells C77 and C78 to the flip-flop circuits FF79 and FF80 is a clock path CP710 and that a signal path for a clock signal CLK from input through the cell C71, OR gate G73, selector S74, and cell C81 to the flip-flop circuits FF82 and FF83 is a clock path CP720. Moreover, it is assumed that a signal path for a test clock signal TCK from input through the cell C75, selector S72, and cells C77 and C78 to the flip-flop circuits FF79 and FF80 is a clock path CP810 and that a signal path for a test clock signal TCK from input through the cell C75, selector S74, and cell C81 to the flip-flop circuits FF82 and FF83 is a clock path CP820.
As stated above, conventionally, optimization has usually been performed in one of a plurality of clock modes to determine the layout when a circuit having these clock modes is designed. With the above circuit, for example, the layout has generally been determined by adjusting clock skews so that normal operation will be realized by use of a clock signal CLK for normal operation. Therefore, the clock paths CP710 and CP720 are taken into consideration to adjust clock skews. However, in reality operation on the clock paths CP810 and CP820 by a test clock signal TCK must also be guaranteed. Therefore, the clock paths CP810 and CP820 must also be taken into consideration to adjust clock skews.
When this circuit operates in the other clock mode, a path on which a new timing error occurs may appear. Conventionally, in such a case a designer has manually performed an adjustment by inserting or changing cells with clock skews on all paths taken into consideration. With some sophisticated LSIs in which clock signals are used in a complicated manner, however, it is very difficult to cause clock timing on all paths to match in operation in all clock modes. Moreover, if clock skews are in an unbalanced state, there are many cases where a significant change in circuit is needed to correct a setup/hold error between flip-flops. In these cases a circuit correction, buffer insertion, and the like must be made in many places. Therefore, manual operations by a designer needs a great many man-hours, resulting in very low efficiency in operations.